U.S. patent application Ser. No. 915,390, filed 14 June 1978 in the name of H. S. Lee, and now abandoned, discloses making an electrically reprogrammable semiconductor memory of insulated gate field effect transistors (IGFETs) having polycrystalline silicon floating and control gates. In such transistors, the floating gate is insulatingly sandwiched between the control gate and the surface of the transistor channel region. The floating gate is charged and discharged by applying an apprpriate electrical bias between the control gate overlying the sandwiched gate and the channel region. The sandwiched floating gate has no low resistance electrical connection to it. Hence, it electrically and physically floats above the IGFET channel region. No continued application of electrical power is required to maintain charge on the floating gate. Accordingly, the charge is considered to be nonvolatile.
Floating gates have been negatively charged by avalanche injection and discharged by ultraviolet or x-ray irradiation or by complex capacitance effects. It also is known to discharge them by control gate-channel electrical bias. Avalanche injection charging of the floating gate can be done at a reasonably low potential of 20-40 volts only if the oxide thickness below the floating gate is less than about 100 angstroms. It is difficult and costly to produce satisfactory oxide coatings that are so thin.
U.S. Ser. No. 915,390 Lee proposes making both the floating gate and the control gate of polycrystalline silicon, hereinafter referred to as polysilicon. In such instance, oxide thickness under the floating gate need not be below about 100 angstroms. It can be 1000 angstroms. Moreover, the floating gate can be both charged and discharged merely by reversing polarity of a 20-40 volt potential applied between the control gate and the IGFET channel. Hence, it is easier to manufacture and easier to operate. On the other hand, the charge/discharge polarity reversal required individual IGFET isolation in a memory matrix. Individual IGFETs could be disposed in their own PN junction isolated pocket. However, this required extra masking and processing steps, and attendant yield losses, to produce the isolation.
The U.S. Ser. No. 915,390 type of device thus offers manufacturing advantages and disadvantages. I have found how to obtain the advantages without the disadvantages. I have found how to modify such a device to eliminate polarity reversal on the IGFET, and thereby eliminate the need for device isolation. Hence, no additional masking and processing steps to produce the isolation are necessary.